1. Technical Field
The present invention relates to a semiconductor device provided with a well potential supply region for supplying power to a well region.
2. Background Art
In a semiconductor device of the related art, there is provided a well potential supply region for supplying power to a well region in the vicinity of an active transistor for the purpose of controlling well potential, in other words, for the purpose of preventing latch-up. Furthermore, the “active transistor” refers to a transistor that contributes to a desired function of a circuit using the operation characteristic of the transistor.
FIG. 12 is a diagram showing an example of a layout of a semiconductor device of the related art, in which a well potential supply region is provided. In the configuration of FIG. 12, standard cell arrays in which a plurality of standard cells are disposed in the horizontal direction of the drawing are disposed by being arranged in the vertical direction of the drawing. In addition, in the standard cell array in the center, well potential supply cell VSC is inserted. VSCN is a well potential supply region (TAP region) for supplying well potential to an N-type well, in which N-type impurities are implanted and VSCP is a well potential supply region for supplying well potential to a P-type well, in which P-type impurities are implanted.
Refer to Unexamined Japanese Patent Publication No. 2008-235350, Unexamined Japanese Patent Publication No. 2007-12855, Unexamined Japanese Patent Publication No. 2001-148464, and Unexamined Japanese Patent Publication No. 2009-32961, for example.